Managing wasted active power in processors based on loop iterations and number of instructions executed since last loop

ABSTRACT

Methods of managing wasted active power of processors in computer systems and other electronic devices are disclosed. In one aspect, a method may include counting a number of times that a processor has performed an instruction loop. Then, a determination may be made whether the number of times that the processor has performed the loop is greater than one or more thresholds or other given values. Next, a limit may be imposed on the power of the processor if the number of times that the processor has performed the loop is greater than at least one of the thresholds or given values. Logic to perform such methods is also disclosed, as are systems suitable for incorporating such logic.

BACKGROUND

1. Field

Embodiments of the invention relate to computer systems. In particular,embodiments of the invention relate to power management in computersystems.

2. Background Information

Many modern computer systems include both a main processor and one ormore co-processors. Examples of suitable co-processors include, but arenot limited to, math, graphics, audio, storage, and other bus-masteringinput/output processors known in the arts.

The main processor and co-processor may perform processing in parallel.For example, the main processor may provide pointers, instructions, anddata to the co-processor, such as, for example, by storing them in afirst-in-first-out (FIFO) buffer, linear/circular queue, or otherstorage device. The co-processor may process the instructions and datain parallel with the processing performed by the main processor. Theco-processor may then provide status information to the main processor.For example, the co-processor may have one or more status registers ormemories through which it may provide completions, interrupts, failures,or other execution status information. There are various known ways inwhich the main processor and co-process may exchange status information.

Including one or more of such co-processors generally tends to improvesystem performance. For example, the co-processor may help to provideincreased parallelism and/or help to offload tasks from the mainprocessor. In some cases, the co-processor may be better suited atperforming the offloaded tasks than the main processor.

However, in certain situations, the execution of the main processor mayneed to wait on the execution of the co-processor. For example, the mainprocessor may need to wait for a dependent operation to complete withinthe co-processor in order to proceed. This may tend to be exacerbatedwhen the main processor operates significantly faster than theco-processor. As another example, the work-around for some bugs mayinvolve flushing the queue of the co-processor before taking furtheractions. In such example scenarios, the main processor may stall waitingfor the co-processor to complete its tasks.

In certain advanced architectures, the stalled thread may halt, and waitfor an interrupt from the co-processor to wake it up. In certainhighly-threaded processor architectures, execution may potentiallycontinue with other threads while waiting for the interrupt. Howeversuch event based synchronization is not always available. For example,legacy code may not support multi-threading or programmers may not takethe extra effort to implement such multi-threading. As another example,certain processes, such as, for example, critical processes and/orprocesses that do not support re-entrancy, may need to continue untilcomplete and may not allow for the possibility of introducing aninterrupt. Still other environments simply do not allow for interruptionand/or weren't designed for such threadedness. Accordingly, in somecases, the main processor may repeatedly execute a polling loop wherethe main processor may repeatedly execute a loop of instructions orotherwise await status of the co-processor for an indication that thework has been completed.

Such polling loops may occupy or busy the main processor. Someprocessors, such as, for example, those employed in laptops and otherbattery powered computing devices, may have multiple differentoperational power states, including faster, higher-powered states forrapid execution, and slower, lower-powered states to conserve powerand/or reduce heat generation. The polling loops may be performed whilethe main processor is operating in a relatively high power state. Insome instances the loops may potentially contribute to promotion of themain processor from a lower to a higher power state.

However, having the main processor in a higher power state during suchpolling loops may not significantly speed up execution, since theexecution of the main processor may be waiting on the execution of theco-processor to continue. Faster polling of the co-processor for statusmay not cause the co-processor to complete processing any faster.Rather, the higher power state of the processor and/or the fasterpolling may unnecessarily waste power and produce heat.

Furthermore, laptops and other computer systems tend to have limitedcooling capabilities that are shared by the main processor,co-processor, and other components. Excess heat produced by onecomponent, such as, for example, a main processor, may reduce the amountof cooling available to other components, such as, for example, theco-processor, which may cause the other component to reach its thermallimit faster. This may potentially cause or result in a reduction inperformance of the component or co-processor. Accordingly, in somesituations, the excess heat produced by the main-processor during atight polling loop waiting on the co-processor may result in heating anda corresponding reduction in performance of the co-processor on whichthe main processor is waiting. This may tend to increase the duration ofthe loop and compound the problem.

Power savings and/or heat reduction may potentially be achieved if theprocessor is placed in relatively lower power states during such loops.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The invention may best be understood by referring to the followingdescription and accompanying drawings that are used to illustrateembodiments of the invention. In the drawings:

FIG. 1 is a block flow diagram of a method of managing power of aprocessor, according to one or more embodiments of the invention.

FIG. 2 is a block flow diagrams of a method of managing power of aprocessor using a running hash as a signature, according to one or moreembodiments of the invention.

FIG. 3 is a block flow diagram illustrating remove limit processingusing instructions counted using the method of FIG. 2, according to oneor more embodiments of the invention.

FIG. 4 is a block flow diagrams of a method of managing power of aprocessor using hint instructions and number of instructions as asignature, according to one or more embodiments of the invention.

FIG. 5 is a block flow diagram illustrating remove limit processingusing instructions counted using the method of FIG. 4, according to oneor more embodiments of the invention.

FIG. 6 is a block flow diagram illustrating an alternate embodiment ofdetermining whether a limit is to be imposed on a power of a processorbased in part on loop size, according to one or more embodiments of theinvention.

FIG. 7 is a block diagram of power management logic, according to one ormore embodiments of the invention.

FIG. 8 shows a block diagram of a computer system in which one or moreembodiments of the invention may be implemented.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth.However, it is understood that embodiments of the invention may bepracticed without these specific details. In other instances, well-knowncircuits, structures and techniques have not been shown in detail inorder not to obscure the understanding of this description.

FIG. 1 is a block flow diagram of a method of managing power of aprocessor, according to one or more embodiments of the invention. In oneaspect, the method may be performed in real time by hardware, software,or a combination, during execution of instructions by a main processorin order to reduce power consumption and limit heat generation duringpolling loops where the main processor executes a loop of instructionsand awaits results of a co-processor or other component of the computersystem.

Initially, a number of times a processor has performed a loop may becounted, at block 101. In one or more embodiments of the invention, asignature may be generated for the loop and used to count the number oftimes the loop has been performed. In various embodiments of theinvention, the signature may include a hash generated by a hashfunction, a checksum, or a count of the number of instructions in theloop, although the scope of the invention is not limited in thisrespect.

Then, a determination may be made whether the number of times theprocessor has performed the loop is greater than one or more thresholdsor other given values, at block 102. In one or more embodiments of theinvention, the values may include predetermined values, although this isnot required. In one or more embodiments of the invention, multi-stagedpower limits may be implemented by comparison to multiple progressivelyincreasing thresholds that are increasingly indicative that the mainprocessor is in a polling loop awaiting results of the co-processor.

Next, a limit may be imposed on the power of the processor if the numberof times the processor has performed the loop is greater than at leastone of the given values, at block 103. Imposing a limit on the power ofthe processor may include imposing a limit on the frequency and voltageof the processor or one or more cores, functional units, circuits, orother portions thereof, and/or turning off or disabling one or morecores, functional units, circuits, or other portions of the processor.

This may help to consume power, such as, for example, battery power.This may also help to allow a co-processor or other component to utilizemore of the shared cooling capabilities of the system by reducing theheat generated by the processor while the processor is engaged in theloop and waiting on results from one or more other components.

After placing at least one limit on the power of the processor, adetermination may be made whether a number of instructions executed in arun, such as, for example, since the last loop, or since the last loopindication instruction, is greater than a second given threshold orvalue. In one aspect, this threshold or value may be predetermined,although this is not required. In one or more embodiments of theinvention, the second given value or threshold may be larger than anaverage or typical polling loop size, such as, for example, based onprior execution, simulation, history, or other modes of estimation. Asone example, the second given value or threshold may equal or exceed arunning toll or record of the largest number of instructions executed ina loop performed thus far in execution by the processor. As anotherexample, the second given value or threshold may be a number that islarger than expected for polling loops based on simulation, history, orother modes of estimation.

Next, the limit imposed on the power of the processor may be removed, orat least reduced, if the number of instructions executed is greater thanthe second given value, at block 105. In this way, since the processorhas likely executed the polling loop, the limits may be removed so thatthe processor may resume performing useful work at high speed.

FIGS. 2-3 are block flow diagrams of a method of managing power of aprocessor using a hash, or other electronic signature computed with afunction, according to one or more embodiments of the invention. Themethod may be performed for each instruction of code executed orotherwise processed.

The method may commence at block 220. At block 220, a new instruction ofcode may be fetched, retrieved, loaded, or otherwise received forprocessing in an instruction pipeline of a main processor. In variousembodiments of the invention, the instruction may be received from astatic memory, such as, for example, a random access memory (ROM) orflash memory, or from a main system memory, or from a disc, by theprocessor.

The instruction may have an opcode that specifies an operation to beperformed, potentially immediate data, and one or more data addresses.The immediate data may represent fixed data that is natively includedwith an instruction as opposed to indirect data in a register or otherstorage location identified by the instruction, which may potentiallychange during a loop. The immediate data is fixed by the instructioncode and therefore may be the same each time a loop is executed. By wayof example, the data addresses may include source data addresses,destination data addresses, and combinations thereof. The addresses mayinclude addresses in a register, system memory, other storage locations,and combinations thereof. The addresses may help to avoid confusing astalled polling loop for a pattern search routine or other thread thatuses indirect addressing, which may be performing useful work, but isnot required.

The method may advance from block 220 to block 221. At block 221, theinstruction may be added to or incorporated to a running hash computed,calculated, or otherwise generated for preceding instructions in theloop. In one or more embodiments of the invention, information from thecurrent instruction may be provided as input to a hash function, whichmay generate the running hash based in part on the input for the currentinstruction and based in part on information from previously encounteredinstructions in the loop. The hash function has the followingproperties: (a) if hashes (outputs) generated using the same hashfunction are different, then the corresponding inputs to the hashfunction are different; and (b) the equality of hashes (outputs of thefunction) suggests or strongly suggests (but does not necessarilyguarantee) the equality of the corresponding inputs to the hashfunction. For example, in one or more embodiments of the invention,“suggests” may mean that there is at least a 90% likelihood of theequality of the inputs, and “strongly suggests” may mean that there isat least 99% likelihood of the equality of the inputs, although otherembodiments are not limited in this respect. Other functions havingthese properties are also suitable. The running hash may represent arelatively unique electronic signature or fingerprint to represent oridentify the current and preceding instructions. The relatively uniquesignature or fingerprint may be used to identify a loop from otherloops, since it is recognized that various different types of loops,such as, for example, simple loops, loops with inner loops, loops withforward skips, and loops with inner sub-routines, and combinations ofsuch loops, may potentially be encountered.

In one or more embodiments of the invention, the information from theinstruction that may be provided as input to generate the running hashmay include the opcode, the immediate data, and the data addresses ofthe instruction. Notice that, in one or more embodiments of theinvention, the indirect data stored in the data addresses specified bythe instruction may not be provided as input to generate the runninghash, since this may potentially vary within a loop. Variance may causethe running has generated for repeat executions of the same loop tovary, which may tend to hinder detection of repeat executions of thesame loop. Rather, the hard coded instruction data may be used togenerate the running hash.

Various hash functions are suitable. Examples of suitable hash functionsinclude, but are not limited to, DJB, DEK, ELF, and CRC32, although thescope of the invention is not limited to just these particular examples.In one aspect, the hash function may favor lightweight inner corealgorithm, may be capable of handling large amounts of byte code withfew collisions, and may be suitable for hardware implementation,although this is not required. Alternatively, a hash function is notrequired and other functions, such as, for example, checksums, errorcorreaction codes, cyclic redundancy checks, Reed-Solomon codes, and thelike, may optionally be used. The method may advance from block 221 toblock 222. At block 222, a determination may be made whether theinstruction is a reverse branch instruction.

There are various ways to determine whether or not an instruction is areverse branch instruction. As one example, in the IA32 and IA64instruction set architectures, a jump instruction with an address lessthan the current instruction address may be inferred to be a reversebranch instruction. As another example, a loop instruction specifying anon-zero reverse instruction offset (or an instruction address less thanthe current instruction pointer) may represent a reverse branchinstruction. Other instructions that reverse execution flow or that areknow to be associated with loops in these or other instruction setarchitectures may also be determined to be reverse branch instructions.

If the instruction is not a reverse branch instruction (i.e., “no” isthe determination at block 222), then the method may advance to block223. At block 223, a running counter representing the number ofinstructions processed since the last reverse branch instruction wasencountered (num-inst) may be incremented, or increased by one, toaccount for the current instruction.

The method may advance from block 223 to block 224. Block 224 mayrepresent remove limit processing that may be used to determine whethera limit has been imposed on the maximum power of the processor and ifthat limit should be removed, or at least reduced. In one or moreembodiments of the invention, this determination may be made based, atleast in part, on the value of the running counter representing thenumber of instructions processed since the last reverse branchinstruction was encountered (num-inst). For example, in variousembodiments of the invention, if num-inst is greater than a threshold,such as, for example, a typical loop size or the loop size empiricallyobserved to provide useful processing work, or the largest loop sizeencountered thus far, then the limit may be removed, or at leastreduced. FIG. 3, which will be discussed below, illustrates exampleremove limit processing, according to one or more embodiments of theinvention, although this particular processing is not required.

Alternatively, if the instruction is a reverse branch instruction (i.e.,“yes” is the determination at block 222), then the method may advance toblock 226. Block 226 is one of a set 225 of blocks 226, 227, 228, 229,and 230, which illustrate an embodiment of determining whether thereverse branch instruction is part of an already detected and/or storedloop or part of a new loop to be stored.

During previous performances of the method, multiple different loops maybe encountered. A unique running hash may be created for each of thedifferent loops up to the point of the associated reverse branchinstruction for each of these loops. These unique running hashes may bestored, such as, for example, in a table, list, stack, data structure,record, or other storage. See, for example, the discussion of block 229a few paragraphs below. Each of these unique running hashes may uniquelyidentify its corresponding loop. If a comparison indicates that tworunning hashes equal or match, then by inference this may representrepeat executions of the same loop.

At block 226, a determination may be made whether the running hashgenerated up to this point for the current reverse branch instruction(the current loop), is equal to or otherwise matches a running hashstored in the table, list, stack, data structure, record, or otherstorage, which is indexed by a current value of a counter (i). In theillustrated embodiment, the counter (i) may initially have or beassigned a lowest value, such as, for example, zero or one, andthereafter may be incremented, although the scope of the invention isnot so limited.

If the running hashes do not match (i.e., “no” is the determination atblock 226), then the method may advance to block 227. At block 227, adetermination may be made whether the counter (i) indexes the last entryin the table, list, stack, data structure, record, or other storage.

If the counter (i) does not index the last entry in the storage (i.e.,“no” is the determination at block 227), then the method may advance toblock 228. This may mean that there are additional running hashes in thedata structure that have not yet been compared to the running hash forthe current branch instruction at block 226. Accordingly, at block 228,the value of the counter (i) may be incremented or increased by one.This may index or otherwise select the next running hash in the datastructure. The method may then revisit block 226.

Alternatively, if the counter does index the last entry in the table orother storage (i.e., “yes” is the determination at block 227), then themethod may advance from block 227 to block 229. At block 229, therunning hash for the current branch instruction may be stored in anavailable location in the table, list, stack, data structure, record, orother storage. That is, since at this point the running hash for thecurrent reverse branch instruction has been compared to all of therunning hashes for previously encountered loops detected and stored, andsince not match has been found, it may be inferred that the currentreverse branch instruction has not previously been encountered and/orthat the loop associated with the current reverse branch instruction isa new loop to be added to the list or table or otherwise stored.

The method may then advance from block 229 to block 230, where themethod may terminate. Since the present loop is a new loop, there is noindication yet that the loop has or will stall, and accordingly, nolimiting of the power state may be justified at this point. Note thatthe method terminates for the current instruction, and that anotherinstance of the method may be performed, starting at block 220, for thenext instruction received for processing.

Accordingly, the method may loop through blocks 226, 227, and 228 zeroor more times until either all of the entries in the storage have beencompared to the running hash for the current branch instruction andeither a match has been found at block 226, in which case processing mayadvance from block 226 to block 231, or else the last entry in thestorage has been reached without a match, in which case processing mayadvance from block 227 to block 229.

Referring again to block 226, if the running hashes compared are equalor otherwise match (i.e., “yes” is the determination at block 226), thenthe method may advance to block 231. An equality or match between theunique running hash generated for the current reverse branch instructionand a unique running hash stored for a previously encountered loop mayindicate or allow it to be inferred that the loop corresponding to thecurrent reverse branch instruction is the same as a previouslyencountered loop corresponding to the running hash stored in the tableor other storage.

At block 231, the value of the running counter (num-inst) previouslydiscussed above in connection with block 223, may be stored in thetable, list, stack, data structure, record, or other storage at the sameentry or index as the matching running hash. Accordingly, for eachindex, a running hash value and a value of num-inst may be stored.Recall that the counter num-inst may represent the number ofinstructions processed since the last reverse branch instruction wasencountered. The size of num-inst represents the size or number ofinstructions in the loop. The values of this counter (num-inst) may beused in connection with block 349 of FIG. 3, which will be discussedfurther below.

The method may advance from block 231 to block 232. At block 232 a loopcounter indexed by the current value of the counter (i) may beincremented or increased by one. The loop counter may represent thenumber of times the loop corresponding to the current reverse branchinstruction has been performed. Accordingly, this may count the numberof times the loop associated with the current instruction has beenperformed. The value of the loop counter may optionally be stored at thesame index as the matching running hash, although this is not required.Alternatively, one or more single non-arrayed loop counter(s) withpotentially different names may optionally be employed.

The method may then advance from block 232 into one or more of a set 233of blocks 234-239, which may illustrate an embodiment of determiningwhether a limit is to be imposed on the power of a processor. Thedetermination may involve a series or progression of one or morecomparisons to given thresholds or values and progressive conditionedapplication of power state limits based at least in part on thecomparisons to the thresholds or values.

In particular, the method may advance from block 232 to block 234. Atblock 234, a determination may be made whether the value of the loopcounter indexed by or corresponding to the current reverse branchinstruction is greater than a first lowest-valued threshold (T1). T1 mayhave a value suitable for the particular implementation. Representativevalues that are suitable for certain embodiments of the invention willbe discussed further below.

If the loop counter is not greater than T1 (i.e., “no” is thedetermination at block 234), then limiting the maximum power of theprocessor may not yet be justified. In such a case, the method mayadvance to block 240, which will be discussed further below.

Alternatively, if the loop counter is greater than T1 (i.e., “yes” isthe determination at block 234), then the method may advance from block234 to block 235. At block 235 another determination may be made whetherthe loop counter is greater than a second middle-valued threshold (T2).T2 may be greater than T1.

If the loop counter is not greater than T2 (i.e., “no” is thedetermination at block 235), then the method may advance to block 236.At block 236 a first highest-powered limit or ceiling may be imposed onthe maximum power of the processor, and the power of the processor maybe reduced to below the first limit. In various embodiments of theinvention, the power state may be limited through hardware, such as, forexample, fuses, controls, or other circuits, or through software. Invarious embodiments of the invention, limiting the power may includereducing frequency, voltage, turning off certain circuits, such as, forexample, functional units or cores of a multi-core processor, andcombinations thereof. Various ways of reducing power known in the artsare suitable. The method may then advance to block 240, which will bediscussed further below.

Alternatively, if the loop counter is greater than T2 (i.e., “yes” isthe determination at block 235), then the method may advance to block237. At block 237, yet another determination may be made whether theloop counter is greater than a third highest-valued threshold (T3). T3may be greater than T2.

If the loop counter is not greater than T3 (i.e., “no” is thedetermination at block 237), then the method may advance to block 238.At block 238 a second, medium-powered limit or ceiling, may be placed onthe maximum power of the processor, and the power of the processor maybe reduced to below the second, lower limit. The second limit mayrepresent a lesser total operational power than the first limit. Themethod may then advance to block 240, which will be discussed furtherbelow.

Alternatively, if the loop counter is greater than T3 (i.e., “yes” isthe determination at block 237), then the method may advance to block239. At block 239, a third, lowest-powered limit or ceiling, which maybe lower than the first and second limits, may be placed on the maximumpower of the processor, and the power of the processor may be reduced tobelow the third, still lower limit. The application of one or more ofthe first, second, or third limits, may help to reduce power consumptionand heat generation while the processor is within a polling loop orotherwise idle awaiting completion by the co-processor. The method maythen advance to block 240, which will be discussed further below.

Now, the scope of the invention is not limited to any known values ofT1, T2, or T3. Suitable values for these thresholds may vary widely duein part to such factors as the wide variety of execution rates ofprocessors on which embodiments of the invention may be implemented, anddue in part to the ever increasing execution rates of processors. Thatbeing said, a few possible, non-limiting, values may help to illustratecertain concepts. In one or more embodiments of the invention, T1 mayhave a value that is within two orders of magnitude of 100,000 (i.e.,1,000≦T1≦10,000,000), T2 may have a value that is within one order ofmagnitude of 10,000,000 (i.e., 1,000,000≦T2≦100,000,000), and T3 mayhave a value that is within one order of magnitude of 100,000,000 (i.e.,10,000,000≦T3≦1,000,000,000). However, these values are merelyillustrative, and non-limiting, and the scope of the invention is notlimited to just these particular values. Other values may be appropriatefor a particular implementation, especially if the speed of execution ofthe processor differs considerably from that of present day processorsmanufactured by Intel Corporation, such as, for example, a present dayIntel® Core™2 Duo processor.

Referring again to the figure, the method may advance from either ofblocks 234, 236, 238, or 239 to block 240. At block 240, the value ofthe counter (num-inst) previously discussed above in connection withblocks 223 and 231, may be cleared or set to zero. This may clear thecount or tally of the number of instructions processed since the lastreverse branch instruction. In this way, num-inst will start again withone for the first instruction received in the re-execution of the loop.

The method may then advance from block 240 to block 241, where themethod may terminate. As before, the termination of the method may onlyrepresent the termination of the method for the current instruction, andanother instance of the method may be performed, starting at block 220,for the next instruction received for processing.

Recall that the method may advance from block 223 to block 224, whichmay represent a promotion stage of the method, wherein a determinationmay be made whether or not to remove a previously imposed limit on themaximum power of a processor.

FIG. 3 is a block flow diagram illustrating remove limit processing 324,according to one or more embodiments of the invention. The method maydetermine whether a limit on processor power has been imposed, and if sowhether the limit may be removed, or at least reduced.

The method may commence and advance to block 346. At block 346, adetermination may optionally be made whether a limit or ceiling has beenpreviously imposed on the maximum power of a processor.

If a limit has not been imposed (i.e., “no” is the determination atblock 346), then the method may advance to block 347, where the methodmay end. This determination, which is optional, may help to improveefficiency by avoiding further processing described below when no limiton processor power is presently imposed.

Alternatively, if a limit has been imposed (i.e., “yes” is thedetermination at block 346), then the method may advance to block 349.At block 349, a determination may be made whether the running counterrepresenting the number of instructions processed since the last reversebranch instruction was encountered (num-inst) is greater than a secondgiven threshold or value, which may be larger than a typical pollingloop size.

In one or more embodiments of the invention, the second given thresholdor value may be the largest value of num-inst stored in the table, list,stack, record, or other storage. Recall that the number of instructionsin each loop (num-inst) may be stored in the table or other storage foreach loop previously encountered at block 231. By way of example, acomparison may be made against all of the values of num-inst stored inthe table, or as another example the values of num-inst stored in thetable may be sorted and the largest value identified and used forcomparison.

Alternatively, in one or more embodiments of the invention, the secondgiven threshold or value may be an arbitrarily large threshold or value,such as, for example, a number larger than expected for loops that tendto stall and produce little if any useful work. This may be estimated orempirically determined for a particular implementation, such as, forexample, by examining the sizes of loops that tend to stall the mainprocessor.

Referring again to block 349, if the current running counter num-inst isnot greater than the given threshold or value (i.e., “no” is thedetermination at block 349), then the method may advance to block 353,where the method may end. Since the current running counter num-inst isnot greater than the given threshold or value, execution may still bewithin one or more of the previously encountered loops, and the existinglimits imposed on the processor power may have merits.

Furthermore, sometimes large loops may be performing useful processingeven when they are repeated a large number of times. So a potentialadvantage is that power may not be unnecessarily limited in such largeloops having relatively more instructions than other loops. Conversely,excessive repeated execution within small sized loops is oftenindicative of wasted work that need not use the full performance orcomputational power of the processor.

Alternatively, if the current running counter num-inst is greater thanthe given threshold or value (i.e., “yes” is the determination at block349), then the method may advance to block 350. At block 350, acurrently imposed limit on the power of the processor may be removed, orat least reduced by one or more levels. Since the current runningcounter num-inst is greater than the value and/or greater than thenumber of instructions in the largest loop presently encountered andcurrently indicated in the list, table, or other storage, execution mayhave broken out of all of the previously encountered loops currentlyindicated in the storage. In such a case, it may be appropriate toremove or reduce the limits that have been imposed based on these loops.

The method may advance from block 350 to block 351. At block 351, theentries in the table, list, stack, data structure, record, or otherstorage may be cleared or deleted. Then, at block 352, the loop counterrepresenting the number of times the loops previously encountered andpreviously referred to in connection with block 232 may be cleared orzeroed. The method may then end at block 353.

Now, the scope of the invention is not limited to using hash functionsor the other functions described above. In one or more alternateembodiments, one or more hint instructions may be included in a loop,and the number of instructions counted between repeat encounters of thehint instructions may be used as a signature to identify the loop andcount the number of times the loop is performed.

A non-limiting example of a hint instruction, HINT_POLLING( ), which maybe included in code is shown below.

void WaitForFlipDone(. . .) { // . . . while ((*pSwTag != *pHwTag) &&(MaxCount < 0x10000000)) { HINT_POLLING( ); MaxCount++;  } // . . . }

In this particular case, the hint instruction is included in a pollingloop in which the main processor may wait on a snooped write into amemory location through which the co-processor may indicate that aspecific task has been completed for synchronization of dependencies.Hint instructions may similarly be included in other polling loops bycompilers, coders, or programmers. Such hint instructions may be placedat various locations within the loops as long as at least one hintinstruction is included in each loop.

The number of instructions encountered between hint instructions may becounted, such as, for example, including a counter that is incrementedeach time an instruction that is not a hint instruction is encountered.If the same number of instructions between hint instructions is repeateda large number of times, this may suggest or strongly suggest repeatperformance of a tight polling loop.

In one or more embodiments of the invention, additional information mayoptionally be combined with the counted number of instructions toprovide additional uniqueness or distinctiveness to distinguish one loopfrom another, although this is not required. Examples of suitableadditional information includes, but is not limited to, a hash, a uniqueidentifier generated by the coder/compiler or otherwise included withthe hint instruction, a value or other indication of the instructionbefore the hint instruction, or some other additional information.

FIGS. 4-5 are block flow diagrams of an alternate method of managingpower of a processor using hint instructions, according to one or moreembodiments of the invention. FIG. 4 bears a number of similarities toFIG. 2, and FIG. 5 bears a number of similarities to FIG. 3. Forconvenience terminal portions of reference numerals have been repeatedamong FIGS. 2-5 to indicate corresponding or analogous operations. Forexample, the reference numerals 420, 422′, 423, 424, 425, 426′, 427′,428, 429′, 430, 432, 433, 434, 435, 436, 437, 438, 439, 440, and 441correspond to or are analogous to the reference numerals 220, 222, 223,224, 225, 226, 227, 228, 229, 230, 232, 233, 234, 235, 236, 237, 238,239, 240, and 241, respectively. Likewise, the reference numerals 546,547, 549, 550, 551, 552, and 553 correspond to or are analogous to thereference numerals 346, 347, 349, 350, 351, 352, and 353, respectively.To avoid obscuring certain concepts, the following discussion will focusprimarily on the different and/or additional operations and aspects. Inthis regard, primes (′) are included alongside the reference numerals todesignate relatively more different operations, which will be discussedin further detail below.

Referring now to FIG. 4, the blocks with primes (′) will be discussed ingreater detail. After receiving an instruction at block 420, adetermination may be made whether the instruction is a hint instruction,at block 422′. By way of example, the hint instruction may be named ahint instruction or otherwise known ahead of time to be a hintinstruction.

If the instruction is not a hint instruction, then a running counterrepresenting the number of instructions processed since the last hintinstruction was encountered (num-inst′) may be incremented, or increasedby one, to account for the current non-hint instruction. Num-inst′ isdistinguished from the counter num-inst discussed above in that itcounts the number of instructions between hint instructions, instead ofbetween reverse branch instructions.

Alternatively, if the instruction is a hint instruction, then the methodmay advance to a slightly different approach 425′ of determining whetherthe current instruction is part of an already detected loop or new loop.At block 426′, a determination may be made whether the num-inst′ for thecurrent instruction matches the i-th indexed num-inst′ in a table, list,stack, data structure, record, or other storage. Similar to before,during previous performances of the method, multiple different loops maybe encountered. For each encountered loop, the number of instructionsencountered between hint instructions (num-inst′) may be stored in thestorage. The num-inst′ may serve as a relatively unique fingerprint toidentify the loop, particularly when the loop has a large number ofinstructions.

If the num-inst′ do not match (i.e., “no” is the determination at block426′), then a determination may be made whether the counter (i) indexesthe last entry in the table, list, stack, data structure, record, orother storage, at block 427′. If the counter (i) does not index the lastentry, then the counter may be incremented at block 428, and processingmay revisit block 426′.

Otherwise, if the counter (i) indexes the last entry, then num-inst′ maybe stored for the current hint instruction in the storage, at block429′. The method may then end, at block 480.

Other aspects of the method illustrated in FIGS. 4-5 may optionally besimilar to that those shown and described for the method illustrated inFIGS. 2-3. To avoid obscuring the description, these aspects will not berepeated.

Now, in some cases, repeatedly performed small loops may tend to involvewasted work more than repeatedly performed large loops. In some cases,large loops, even if repeatedly performed many times, may actually beperforming useful work that may justify higher processor power. One ormore embodiments of the invention may optionally determine whether ornot to impose limits on the power of a processor and/or determine howmuch limit to impose based in part on loop size.

FIG. 6 is a block flow diagram illustrating an alternate embodiment ofdetermining whether a limit is to be imposed on a power of a processor633 based in part on loop size, according to one or more embodiments ofthe invention. This block flow diagram shows similarity to theprocessing 233 and 433 discussed above. For brevity, the discussionbelow will focus primarily on the differences, and the similarities willnot be repeated. One notable difference is that determining of whetheror not to impose the limit on the power of the processor and/or how muchlimit to impose is based on the size or number of instructions in theloop in addition to the number of times the loop has been performed.

Block 634 of the method may be entered, such as, for example, from block232 or block 432. At block 634, a determination may be made whether theloop counter is greater than a first lowest-valued loop counterthreshold (T1), and num-inst is less than a first highest-valued numberof instructions threshold (N1).

If either or both conditions are false (i.e., “no” is the determinationat block 634), then limiting the maximum power of the processor may notyet be justified. In such a case, the method may exit, such as, forexample, to block 240 or 440.

Alternatively, if both conditions are true (i.e., “yes” is thedetermination at block 634), then the method may advance to block 635.At block 635 another determination may be made whether the loop counteris greater than a second middle-valued loop counter threshold (T2), andnum-inst is less than a second middle-valued number of instructionsthreshold (N2). T2 may be greater than T1, and N2 may be less than N1.

If either or both conditions are false (i.e., “no” is the determinationat block 635), then the method may advance to block 636. At block 636 afirst highest-powered limit or ceiling may be imposed on the maximumpower of the processor, and the power of the processor may be reduced tobelow the first limit. The method may then exit, such as, for example,to block 240 or 440.

Alternatively, if both conditions are true (i.e., “yes” is thedetermination at block 635), then the method may advance to block 637.At block 637, yet another determination may be made whether the loopcounter is greater than a third highest-valued loop counter threshold(T3), and num-inst is less than a third lowest-valued number ofinstructions threshold (N3). T3 may be greater than T2, and N3 may belower than N2.

If either or both conditions are false (i.e., “no” is the determinationat block 637), then the method may advance to block 638. At block 638 asecond, medium-powered limit or ceiling, may be placed on the maximumpower of the processor, and the power of the processor may be reduced tobelow the second, lower limit. The second limit may represent a lessertotal operational power than the first limit. The method may then exit,such as, for example, to block 240 or block 440.

Alternatively, if both conditions are true (i.e., “yes” is thedetermination at block 637), then the method may advance to block 639.At block 639, a third, lowest-powered limit or ceiling, which may belower than the first and second limits, may be placed on the maximumpower of the processor, and the power of the processor may be reduced tobelow the third, still lower limit. The method may then exit, such as,for example, to block 240 or block 440.

The scope of the invention is not limited to any known values of N1, N2,or N3. In one or more embodiments of the invention, N1 may range fromabout 500 to about 2000 instructions, N2 may range from about 100 toabout 500 instructions, and N3 may range from about 2 to 100instructions. However, these values are merely illustrative, andnon-limiting, and the scope of the invention is not limited to justthese particular values.

Accordingly, power of a processor may be managed based on both how manytimes a loop has been performed and the size of the loop.Advantageously, this may help to reduce the number of limits imposed onthe processor when the processor is executing large loops that mayactually be performing useful operations. However, this is optional, andnot required. In one or more embodiments of the invention, power savingsand/or reduction in heat generation may be obtained based on countingthe number of times a loop has been performed without looking at thesize of the loop.

FIG. 7 is a block diagram of power management logic 760, according toone or more embodiments of the invention. The power management logic mayperform one or more of the methods disclosed herein. In one or moreembodiments of the invention, the logic may include hardware, such as,for example, circuitry within a processor or other microelectronicdevice. Alternatively, in one or more embodiments of the invention, thelogic may include software, such as, for example, a routine or other setof instructions of, or interfacing with, an operating system. As yetanother option, in one or more embodiments of the invention, the logicmay include a combination of hardware and software.

The illustrated logic optionally includes signature computation logic721 to compute a running hash or other signature of a loop. Thesignature computation logic may be omitted in embodiments of theinvention, as discussed above in the context of the hint instructions.

Instruction examination logic 722 is coupled with, or otherwise incommunication with, the signature computation logic. The instructionexamination logic may examine the instructions to determine their type.For example, the instruction examination logic may determine whether acurrent instruction being processed is a reverse branch instruction or ahint instruction.

An instruction counter 723 is coupled with, or otherwise incommunication with, the instruction examination logic. The instructioncounter may keep a count of the number of instructions processed sincethe last loop was detected.

Remove limit processing logic 724 is coupled with, or otherwise incommunication with, the instruction counter. The remove limit processinglogic may determine whether to remove or reduce limits previouslyimposed on the power of the processor. As shown, the remove limitprocessing logic may include number instructions/threshold comparisonlogic 749 to compare the number of instructions with a threshold orother value in order to make this determination.

Signature comparison and storage logic 725 is also coupled with, orotherwise in communication with, the instruction examination logic. Thesignature comparison and storage logic may use the signature for thecurrent instruction to determine whether the current instruction is partof an already detected loop or a new loop to be stored.

A storage 762 is coupled with, or otherwise in communication with, thesignature comparison and storage logic to store the loop for the currentinstruction if it is a new loop. Alternatively, a loop counter 732 iscoupled with, or otherwise in communication with, the signaturecomparison and storage logic to keep a count of the number of times theloop has been performed if the current instruction is part of an alreadydetected loop.

Impose limit processing logic 733 is coupled with, or otherwise incommunication with, the loop counter. The impose limit processing logicmay determine whether a limit is to be imposed on the power of theprocessor based on the count of loops available from the loop counter,and if so to impose such a limit. As shown, the impose limit processinglogic may include at least one loop counter/threshold comparison logic734 to compare the number of times the loop has been performed with athreshold in order to make this determination.

FIG. 8 shows a block diagram of a computer system 880 in which one ormore embodiments of the invention may be implemented. The computersystem may include, but is not limited to, a portable, laptop, desktop,server, or mainframe computer, to name just a few examples. The computersystem represents one possible computer system for implementing one ormore embodiments of the invention, however other computer systems andvariations of the computer system are also possible.

The computer system includes at least one bus 881 to communicateinformation, and a main processor 882 and co-processor 883 coupled withthe bus to process information. Alternatively, other interconnects orserial interconnects besides buses may optionally be used, such as, forexample, PCI Express, or others known in the arts. In one or moreembodiments of the invention, the co-processor and/or the main processormay include a microprocessor available from Intel Corporation, of SantaClara, Calif., although this is not required. In one or more embodimentsthe co-processor and/or the main processor may include multipleprocessor cores working together, although this is not required.

The computer system further includes a main memory 884, such as, forexample, a random access memory (RAM) or other dynamic storage device,coupled with the bus to store information including instructions to beexecuted by the main processor and co-processor. The main memory alsomay be used to store temporary variables or other intermediateinformation during execution of instructions by the processor. Differenttypes of RAM memory that are included in some, but not all computersystems, include, but are not limited to, static-RAM (SRAM) anddynamic-RAM (DRAM). Memory that does not need to be dynamicallyrefreshed is also suitable.

The computer system also includes a non-volatile memory 885, such as,for example, a read only memory (ROM) or other static storage device,coupled with the bus to store static information and instructions forthe processors. In one or more embodiments of the invention, thenon-volatile memory may store the basic input-output system (BIOS).Different types of non-volatile memory that are included in some, butnot all, computer systems include, but are not limited to, Flash memory,programmable ROM (PROM), erasable-and-programmable ROM (EPROM), andelectrically-erasable-and-programmable ROM (EEPROM).

Firmware 887 may optionally be coupled with the bus. The firmware mayinclude a combination of software and hardware. By way of example, thefirmware may include Electronically Programmable Read-Only Memory(EPROM) having instructions or routines stored. The firmware may embedfoundation code, basic input/output system code (BIOS), or the like. Thefirmware may make it possible for the computer system to boot itself.

The computer system includes a chipset 888. The chipset may include aset or group of integrated circuits that work together to provideinterfacing and other functions. In one or more embodiments of theinvention, the chipset may be one of those available from IntelCorporation, although this is not required.

The computer system may also optionally be coupled via the bus with adisplay device 889, such as, for example, a cathode ray tube (CRT) orliquid crystal display (LCD), to display information to an end user. Inone or more embodiments of the invention, such as, for example, in alaptop, the display may be integral with the computer system, althoughthis is not required.

A keyboard 890, or other alphanumeric input device includingalphanumeric and other keys, may optionally be coupled with the bus tocommunicate information and command selections to the processor. In oneor more embodiments of the invention, such as, for example, in a laptop,the keyboard may be integral with the computer system, although this isnot required. Another type of user input device that may optionally beincluded is a cursor control device 891, such as, for example, a mouse,trackball, or cursor direction keys, to communicate directioninformation and command selections to the processor, and to controlcursor movement on the display device.

A network device 892 may also optionally be coupled with the bus.Network devices are included in some, but not all, computer systems.Suitable network devices include, but are not limited to, wired andwireless telephony interfaces, such as, for example, those provided inmodems and network interface cards.

The computer system may also include a power supply 893 to provide powerto the computer system. In one or more embodiments of the invention, thepower supply may include an alternating current (AC) adapter circuit.The AC adapter circuit may allow AC current from an outlet or othersource to be converted to direct current (DC) to power the computersystem.

In one or more embodiments of the invention, the computer system mayrepresent a laptop or else may represent other types of mobile computingdevices. Examples of suitable mobile computing devices include, but arenot limited to, laptop computers, cell phones, personal digitalassistants, and like devices. In such embodiments, the system mayinclude an DC power source, such as, for example, a battery or fuelcell. The battery or fuel cell may power the computer system when ACpower from an outlet is not available. The total power available fromthe battery or fuel cell may be limited. Advantageously, in one or moreembodiments of the invention, the power conserving approaches disclosedherein may allow prolonged use of the computer system while operating onpower from the battery, fuel cell, or other finite source of DC power.

In the following description and claims, the terms “coupled” and“connected,” along with their derivatives, may be used. It should beunderstood that these terms are not intended as synonyms for each other.Rather, in particular embodiments, “connected” may be used to indicatethat two or more elements are in direct physical or electrical contactwith each other. “Coupled” may mean that two or more elements are indirect physical or electrical contact. However, “coupled” may also meanthat two or more elements are not in direct contact with each other, butyet still co-operate or interact or communicate with one another.

In the description above, for the purposes of explanation, numerousspecific details have been set forth in order to provide a thoroughunderstanding of the embodiments of the invention. It will be apparenthowever, to one skilled in the art, that one or more other embodimentsmay be practiced without some of these specific details. In one aspect,other signatures besides hashes, checksums, counts of loop instructions,and others method above may optionally be used. For example, messagedigest functions, string search functions, and other functions used incryptography or error correaction may potentially be used. Theparticular embodiments described are not provided to limit the inventionbut to illustrate it. The scope of the invention is not to be determinedby the specific examples provided above but only by the claims below. Inother instances, well-known circuits, structures, devices, andoperations have been shown in block diagram form or without detail inorder to avoid obscuring the understanding of the description.

Various operations and methods have been described. Some of the methodshave been described in a basic form, but operations may optionally beadded to and/or removed from the methods. For example, in alternateembodiments, fewer or more than the illustrated number of thresholdcomparisons and limits may optionally be utilized. The operations of themethods may also often optionally be performed in different order. Forexample, in one or more alternate embodiments, the running hash mayoptionally only be generated for instructions determined to be reversebranch instructions. As another example, the counter (i) used to indexthe storage may start at a highest value and be decremented thereafter,or entries from the storage may be selected randomly or according toother orders. These are just a few examples. Many modifications andadaptations may be made to the methods and are contemplated.

Certain operations may be performed by hardware components, or may beembodied in machine-executable instructions accessible from and storedon a machine-readable medium, that may be used to cause, or at leastresult in, a circuit programmed with the instructions performing theoperations. The circuit may include a general-purpose or special-purposeprocessor, or logic circuit, to name just a few examples. The operationsmay also optionally be performed by a combination of hardware andsoftware.

One or more embodiments of the invention may be provided as a programproduct or other article of manufacture that may include amachine-accessible and/or readable medium having stored thereon one ormore instructions and/or data structures. The medium may provideinstructions, which, if executed by a machine, may result in and/orcause the machine to perform one or more of the operations or methodsdisclosed herein. Suitable machines include, but are not limited to,computer systems, laptop computers, digital assistants (PDAs), cellulartelephones, and a wide variety of other electronic devices with one ormore processors, to name just a few examples.

The medium may include, a mechanism that provides, for example storesand/or transmits, information in a form that is accessible by themachine. For example, the medium may optionally include recordableand/or non-recordable mediums, such as, for example, floppy diskette,optical storage medium, optical disk, CD-ROM, magnetic disk,magneto-optical disk, read only memory (ROM), programmable ROM (PROM),erasable-and-programmable ROM (EPROM),electrically-erasable-and-programmable ROM (EEPROM), random accessmemory (RAM), static-RAM (SRAM), dynamic-RAM (DRAM), Flash memory, andcombinations thereof.

For clarity, in the claims, any element that does not explicitly state“means for” performing a specified function, or “step for” performing aspecified function, is not to be interpreted as a “means” or “step”clause as specified in 35 U.S.C. Section 112, Paragraph 6. Inparticular, any potential use of “step of” in the claims herein is notintended to invoke the provisions of 35 U.S.C. Section 112, Paragraph 6.

It should also be appreciated that reference throughout thisspecification to “one embodiment”, “an embodiment”, or “one or moreembodiments”, for example, means that a particular feature may beincluded in the practice of the invention. Similarly, it should beappreciated that in the description various features are sometimesgrouped together in a single embodiment, Figure, or description thereoffor the purpose of streamlining the disclosure and aiding in theunderstanding of various inventive aspects. This method of disclosure,however, is not to be interpreted as reflecting an intention that theinvention requires more features than are expressly recited in eachclaim. Rather, as the following claims reflect, inventive aspects maylie in less than all features of a single disclosed embodiment. Thus,the claims following the Detailed Description are hereby expresslyincorporated into this Detailed Description, with each claim standing onits own as a separate embodiment of the invention.

1. A method comprising: counting a number of times a processor hasperformed a loop, wherein said counting the number of times theprocessor has performed the loop includes: (a) generating a signaturefor the loop, wherein said generating the signature comprises using afunction including evaluating the function with instructions of theloop; and (b) using the signature to determine that the loop has beenperformed during said counting; determining whether the number of timesthe processor has performed the loop is greater than one or more values;and imposing a limit on a power of the processor if the number of timesthe processor has performed the loop is greater than at least one of theone or more values; reducing the limit imposed on the power of theprocessor upon determining that a number of instructions executed sincea last loop indication instruction is greater than a value.
 2. Themethod of claim 1, wherein the function has properties that: if outputsgenerated using the function are different, then corresponding inputs tothe function are different; and equality of the outputs generated usingthe function suggests equality of the corresponding inputs to thefunction.
 3. The method of claim 2, wherein the function comprises afunction selected from a hash function and a checksum function andwherein the function comprises a running function that is evaluated withinformation for the instructions of the loop used to evaluate thefunction.
 4. The method of claim 1, wherein said generating thesignature for the loop comprises inputting data from the instructions ofthe loop to the function.
 5. The method of claim 4, wherein the datacomprises one or more of opcodes, immediate data, and addresses,natively included with the instructions.
 6. The method of claim 1,wherein said imposing the limit on the power of the processor comprisesone or more selected from imposing a limit on a frequency of at least aportion of the processor, imposing a limit on a voltage of at least aportion of the processor, and disabling a portion of the processor. 7.The method of claim 1: further comprising determining if a size of theloop is less than one or more size values; and wherein said imposing thelimit on the power of the processor is conditioned on the size of theloop being less than at least one of the one or more size values.
 8. Themethod of claim 1, further comprising the processor continuing toperform the loop while the limit is imposed on the power of theprocessor.
 9. The method of claim 1, wherein imposing the limit on thepower of the processor comprises selectively imposing the limit on thepower of a core of the processor.
 10. The method of claim 1, furthercomprising imposing another lower power limit on the power of theprocessor if the number of times the processor has performed the loop isgreater than another value.
 11. An apparatus comprising: one or morecores of a processor; a counter to count a number of times the processorhas performed a loop; logic to impose a limit on power of the processorif the number of times the processor has performed the loop is greaterthan one or more values; a second counter to keep a second count of anumber of instructions in the loop; and logic to condition the imposingof the limit on the power of the processor on the second count of thenumber of instructions in the loop being less than one or more values,where at least one of the counter, the second counter, the logic toimpose the limit on the power of the processor, and the one or morecores comprises circuitry of the processor.
 12. The apparatus of claim11, further comprising signature computation logic to compute asignature for the loop, wherein the signature computation logiccomprises a function to compute the signature for the loop based oninformation for instructions of the loop and the function havingproperties that: if outputs generated using the function are different,then corresponding inputs to the function are different; and equality ofthe outputs generated using the function suggests equality of thecorresponding inputs to the function.
 13. The apparatus, of claim 12,wherein the function comprises a function selected from a hash functionand a checksum function and wherein the function comprises a runningfunction that is evaluated with the information for the instructions ofthe loop used to compute the signature.
 14. The apparatus of claim 11,further comprising: loop identification logic to identify the loop frompreviously encountered loops using the second count of the number ofinstructions in the loop.
 15. The apparatus of claim 11, furthercomprising instruction examination logic to determine that aninstruction of the loop is a hint instruction and logic to detect theloop using the hint instruction.
 16. The apparatus of claim 11, furthercomprising hardware coupled with the logic to impose the limit, thehardware to perform one or more selected from imposing a limit on afrequency of at least a portion of the processor, imposing a limit on avoltage of at least a portion of the processor, and disabling a portionof the processor.
 17. The apparatus of claim 16, wherein the hardwarecomprises one or more selected from a fuse, a control, and a circuit,and wherein the portion of the processor comprises a core.
 18. A systemcomprising the apparatus of claim 11, wherein the system furthercomprises a direct current (DC) power supply to power the apparatus. 19.An apparatus comprising: a power management logic, the power managementlogic including: a counter to count a number of times a processor hasperformed a loop; logic to impose a limit on power of the processor upondetermining that the number of times the processor has performed theloop is greater than one or more thresholds; and logic to remove thelimit imposed on the power of the processor if a number of instructionsexecuted since a last loop indication instruction is greater than avalue, where the power management logic comprises circuitry.
 20. Theapparatus of claim 19, wherein the power management logic furthercomprises: signature computation logic to compute a signature for theloop by evaluating a function based on information for the loop; andsignature comparison logic to compare the signature computed for theloop with signatures computed for previously encountered loops toidentify the loop during said counting.
 21. The apparatus of claim 20,wherein the signature computation logic is to evaluate a function havingproperties that: if outputs generated using the function are different,then corresponding inputs to the function are different; and equality ofthe inputs to the function are likely equal if the corresponding outputsgenerated using the function are equal.
 22. The apparatus of claim 19,wherein the power management logic further comprises: a second counterto keep a count of the number of instructions in the loop; and loopidentification logic to identify the loop from previously encounteredloops using the count of the number of instructions in the loop.
 23. Theapparatus of claim 19, wherein the logic to remove the limit imposed onthe power of the processor comprises logic to remove the limit if thenumber of instructions executed since the last loop indicationinstruction is greater than a value selected from an average pollingloop size, a value larger than expected for a polling loop, and alargest number of instructions encountered in a loop thus far duringexecution.
 24. The apparatus of claim 19, implemented in a system, thesystem comprising: a dynamic random access memory (DRAM); and a mainprocessor coupled with the DRAM, and wherein the power management logicis part of the main processor.
 25. An article of manufacture comprising:a machine-accessible medium having stored thereon instructions that ifexecuted result in a machine performing operations including, counting anumber of times a processor has performed a loop, wherein said countingthe number of times the processor has performed the loop includes (a)generating a signature for the loop using a function with a propertythat when outputs generated using the function are different then inputsto the function are different, and (b) using the signature to determinethat the loop has been performed during said counting, determiningwhether the number of times the processor has performed the loop isgreater than one or more values, imposing a limit on a power of theprocessor if the number of times the processor has performed the loop isgreater than at least one of the one or more values, determining whethera number of instructions executed since a last loop indicationinstruction is greater than a value, and if the number of instructionsis greater than the value, removing the limit imposed on the power ofthe processor, and wherein the medium comprises at least one of a floppydiskette, an optical storage medium, an optical disk, a CD-ROM, amagnetic disk, a magneto-optical disk, a read only memory (ROM), aprogrammable ROM (PROM), an erasable-and-programmable ROM (EPROM), anelectrically-erasable-and-programmable ROM (EEPROM), a random accessmemory (RAM), a static-RAM (SRAM), a dynamic-RAM (DRAM), a memory, and aFlash memory.
 26. An apparatus comprising: a functional unit of aprocessor, the functional unit including circuitry; a counter to count anumber of times the processor has performed a loop indicated by a hintinstruction, where the apparatus is to identify a loop by a number ofinstructions counted between hint instructions; logic to impose a limiton power of the processor if the number of times the processor hasperformed the loop is greater than one or more values.